Programmer Humor

33755 readers

39 users here now

Post funny things about programming here! (Or just rant about your favourite programming language.)

Rules:

Posts must be relevant to programming, programmers, or computer science.
No NSFW content.
Jokes must be in good taste. No hate speech, bigotry, etc.

founded 5 years ago

MODERATORS

AgreeableLandscape@lemmy.ml

cat_programmer@lemmy.ml

672

Not incorrect. (mander.xyz)

submitted 3 days ago by fossilesque@mander.xyz to c/programmerhumor@lemmy.ml

82 comments fedilink hide all child comments

you are viewing a single comment's thread
view the rest of the comments

[–] white_nrdy@programming.dev 1 points 4 hours ago

Tbf, I am not a grey beard chief engineer, and I strongly prefer VHDL for design. For verification I actually really like SystemVerilog.

VHDL is strongly types, which prevents a lot of issues with types that I've hit with [System]Verilog.

Also, having learned VHDL first, I think it is easier to go from VHDL to Verilog, as opposed to vice versa. And this is mainly because VHDL is stricter.