this post was submitted on 16 Jun 2025
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That seems much too pragmatic for this thread ๐
Possibly but the CPU was pretty crazy. It used "code morphing" to translate x86 instructions to its internal ISA, something that just seems a bit ridiculous to do at the hardware level.
It's way more common than you may realize. Intel & AMD (and other x86 CPU manufacturers of the time) did it before the first Crusoe CPU launched. (2000 according to Wikipedia)
CISC architectures are now seen as inefficient, so all the new ones are RISC and new CISC CPUs just translate the instructions to their intenal RISCier microarchitecture. The CPU's microcode specifies what an instruction translates to.
Oh, absolutely. The thing that is weird is being non-x86 hardware and explicitly implementing the translation layer in hardware that has minimal field configurability (they did have the capability of loading something similar to microcode). It makes sense in some ways (performance being a big one) but, seems like it would be vulnerable to potential changes in the external ISA.
And it was powered by Linus Torvalds!